USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USB 2.0 Device Controller for SoC Designs | Cadence IP
USB 2.0 PHY for SoC Designs | Cadence IP
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
USB Device
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Canovatech - CT20602
HSIC USB 2.0 PHY IP
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
Hi-Speed USB interfacing
ULPI - Kcchao
PCIe/USB/SATA PHY Appilcation example | Renesas
USBPHYC internal peripheral - stm32mpu
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
The USB 2.0 Device IP core | Arasan Chip Systems
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
Having trouble getting USB PHY to work with STM32 : r/embedded
USB 2.0 PHY Verification
The Next-Generation Interconnect | Mouser
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
